# Ripple Carry And Carry Look Ahead Adder

**Ripple Carry And Carry Look Ahead Adder – Logic & Block Diagrams**

** Ripple carry adder and carry look ahead adder** are two different kinds of

**digital binary adders**based on the carry determining technique.

Both adders can add the numbers without any problem. We will briefly discuss both adders in this article.

**What is Ripple Carry Adder?**

**Ripple carry adder** as the name suggest is an adder in which the **carry bit ripple through all the stages of the adder**.

The ripple carry adder contain individual single bit full adders which consist of **3 inputs** (*Augend, Addend and carry in*) and **2 outputs** (*Sum, carry out*). These full adders are connected together in **cascade form** to create a *ripple carry adder*.Fig 1. Ripple carry adder – Full Adder

‘**n**’ full adders combine together to form **‘n’ bit adder**.

‘**n**’ bit adder will have **‘n’ stages** and each stage’s output will depend upon previous stage’s carry out.

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Each stage can calculate the sum at the same time based on the input numbers but the sum will not be valid because the carry in to each of these stages will not be available yet.

For example in a **4-bit adder**, there are 4 stages for each bit addition. The stage 1 being the LSB bit will first evaluate Sum, **C _{out}** and pass

**C**to 2

_{out}^{nd}stage as

**C**.

_{in}Then the 2^{nd} stage will evaluate **C**_{out }and pass it to 3^{rd} stage for calculation and then the 3^{rd} stage will pass it forward to the 4^{th} stage and now the 4^{th} stage can evaluate the **Sum** and **C _{out}**. Now the sum we will get will be a valid output.Fig 2 – Ripple carry adder Stages

In 4 bit adder, the time delay for a valid output is the sum of time delay of 4 full adders, if there is an **‘n’** bit adder, than the time delay will be the sum of time delay of **‘n’** full adders. It means, **higher the bit size of the numbers, the late the answer we will get**. So it is not an efficient design for complex and fast working systems.

The addition could be done as soon as the input numbers (*Augend and addend*) were provide to the adder but because of the carry propagation, **the adder is not able to provide a valid answer** until it reaches the last stage.

The time that the carry took to propagate from the first adder to the last adder is known as **propagation delay**. The major **drawback of Ripple carry adder** is this Propagation delay. But the design of Ripple carry adder is very simple and inexpensive.

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**What is Carry Look Ahead Adder (CLA)**

As we have discussed in the ripple carry adder that the adder takes a time delay to compute sum because the carry was propagated through all the gates from input to output. **To increase the speed of the addition** we need to provide the carry bits used by these adders without the wait for the preceding additions.

So that the addition of all bits is done at the same time.The idea used to compute the carry bits before the addition is known as **Carry look ahead logic**.

Carry look ahead is a digital circuit used for determining the carry bits used by the adder for addition without the wait for the carry propagation. It generates the carry bits for all the stages of the addition at the same time as soon as the input signal (Augend, addend, carry in) is provided.

Due to this technique the adders don’t have to wait for the carry propagation and a valid sum is computed without any delay.

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**Carry Look Ahead Adder (CLA) Logic Diagram**

**Carry look ahead adder’s (CLA) logic diagram** is given below. It contains **3 blocks**; “**P and G generator**”, “**Carrylook ahead**” block and “**adder block**”. Input “**Augend**”, “**Addend**” is provided to the “P and G generator” block whose output is connected with **CLA** and the** adder block**.

CLA block produces carry bits *C _{1}, C_{2}, C_{3}, C_{4}* and provide it to the adder block and evaluate sum

*S*based on these inputs.

_{0}, S_{1}, S_{2},_{ }S_{3},**C**is taken as

_{4 }**C**.Fig 3- Carry look ahead Adder (CLA) logic diagram

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**P and G Generator: Half Adder**

This block consists of half adders used for generating P and G terms of each bit.

This block generate these terms needed for the CLA because the carry depends on it.

**Carry = AB + C _{in }(A XOR B)**

**P = (A XOR B)**: **P** is known as **Carry propagate**, because it propagates the **C _{in}** from previous stage to the next stage.

**G = AB: ** **G** is known as **Carry Generate**, because it can directly generate carry bit without any C_{in}.

P and G terms for a 4 bit number will be:

**P _{0 }= (A_{0} XOR B_{0}) , G_{0} = A_{0}B_{0} ,**

**P _{1 }= (A_{1} XOR B_{1}) , G_{1} = A_{1}B_{1} ,**

**P _{2} = (A_{2} XOR B_{2}) , G_{2} = A_{2}B_{2} ,**

**P _{3} = (A_{3} XOR B_{3}) , G_{3} = A_{3}B_{3} ,**

These P and G terms will be later used by CLA block.Fig 4- P and G Generator: Half Adder

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**Carry Lookahead (CLA) Block Diagram**

**CLA block contains combinational circuit** used to determine the **carry bits**. it takes **Augend, Addend and carry in** **as inputs** and **produce the** **carry bits**.

Consider A, B two numbers being added both 4 bits wide and **C _{0 }**as carry in. And

*C*are the output carry bits.

_{1}, C_{2}, C_{3}, C_{4 }First we will derive C_{1},C_{2},C_{3},C_{4} using the carry equation from full adder.

**Carry = AB + C _{in }(A XOR B)**

** P = (A XOR B) **

**G = AB ,**

**Carry = G + C _{in }P**

So C_{1}, C_{2}, C_{3}, C_{4} will become:

**C _{1 }= G_{0 }+ C_{0}P_{0}**

**C _{2 }= **G

_{1 }+ C

_{1}P

_{1 }= G

_{1}+ (G

_{0 }+ C

_{0}P

_{0})P

_{1}

_{ }= G_{1}+ G_{0 }P_{1}+ C_{0}P_{0}P_{1}**C _{3 }= **G

_{2 }+ C

_{2}P

_{2 }= G

_{2 }+ (G

_{1}+ G

_{0 }P

_{1}+ C

_{0}P

_{0}P

_{1})P

_{2 }

**= G**

_{2 }+ G_{1}P_{2}+ G_{0 }P_{1}P_{2}+ C_{0}P_{0}P_{1}P_{2}**C _{4 }= **G

_{3}+ C

_{3}P

_{3 }= G

_{3}+ (G

_{2 }+ G

_{1}P

_{2}+ G

_{0 }P

_{1}P

_{2}+ C

_{0}P

_{0}P

_{1}P

_{2})P

_{3 }

**= G**

_{3}+ G_{2 }P_{3}+ G_{1}P_{2}P_{3}+ G_{0 }P_{1}P_{2}P_{3}+ C_{0}P_{0}P_{1}P_{2}P_{3}Thus it shows that none of these carry bits depend on their previous stage carry bits. They only need **A** , **B** and **C**_{0.}

Fig 5 – Carry Lookahead (CLA) Block Diagram

This carry look ahead block will generate these carry bits and provide it to the adders block for addition.

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**Adders Block**

As we know that the carry bits will be provided by the CLA block so we don’t need Full adders to evaluate the carry bits. We only need the sum which is:

**S = C _{in}XOR (A XOR B)**

So the sum of each bit will be

**S _{0} = C_{0 }XOR (A_{0} XOR B_{0}) = C_{0 }XOR (P_{0})**

**S _{1} = C_{1 }XOR (A_{1} XOR B_{1}) = C_{1 }XOR (P_{1})**

**S _{2} = C_{2 }XOR (A_{2} XOR B_{2}) = C_{2 }XOR (P_{2})**

**S _{3} = C_{3 }XOR (A_{3} XOR B_{3}) = C_{3 }XOR (P_{3})**Fig 6 -Adder Block

And the last carry C_{4} will be the **C**_{out }of the **CLA full adder**.

**C _{out }= C_{4}**

Full Schematic of Carry look ahead adder is given in figure below.

Fig 7 – Schematic Diagram of Carry look ahead adder

**4-BIT Look-Ahead Carry Generator – 74182 TTL IC Details**

**74182** TTL is **Carry generator** working on** Carry look ahead logic**.

**Inputs**: **P̅ _{0 }= invert of P_{0, }G̅_{0} = invert of G**

_{0 }

**Outputs**:

**C**

_{n}= C_{0, }G̅= C_{OUT}** P̅ _{1}= invert of P_{1}, G̅_{1} = invert of G_{1 }C_{n+x}= C_{1 , }P̅=P̅_{0}P̅_{1}P̅_{2}P̅_{3}**

** P̅ _{2}= invert of P_{2} , G̅_{2} = invert of G_{2 }C_{n+y }= C_{2}**

** P̅ _{3}= invert of P_{3} ,G̅_{3} = invert of G_{3 }C_{n+z}=C**

_{3}

_{}Fig 8: 4-BIT Look-Ahead Carry Generator – 74182 TTL IC Details

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